set-7

301. A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this pointer?

1. Pointers
2. Records
3. Arrays
4. All of the above

302. The 8085 microprocessor responds to the presence of an interrupt:

1. As soon as the TRAP pin becomes high
2. By checking the TRAP pin for high status at the end of each instruction fetch
3. By checking the TRAP pin for high status at the end of the execution of each instruction
4. By checking the TRAP pin for high status at regular intervals

303. Which of the following need not necessarily be saved on a context switch between processes?

1. General purpose registers
2. Program counter
3. Translation look aside buffer
4. All of these

304. If a processor does not have any stack pointer register then:

1. It cannot have subroutine call instruction
2. It can have subroutine call instruction, but no nested subroutine calls
3. Nested subroutine calls are possible, but interrupts are not
4. All sequence of subroutine calls and also interrupts are possible

305. CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged:

1. A hardware interrupt is needed
2. A software interrupt is needed
3. A privileged instruction (which does not generate an interrupt) is needed
4. A non-privileged instruction (which does not generate an interrupt) is needed

306. In the absolute addressing mode:

1. An operand is inside the instruction
2. Address of the operand is inside the instruction
3. Register containing the address of the operand is specified inside the instruction
4. Location of the operand is implicit

307. The capacity of program counter (PC) is:

1. 8 bits
2. 16 bits
3. 12 bits
4. 32 bits

308. The function of program counter (PC) holds:

1. Temporary
2. Memory operand
3. Address for memory
4. Address for instruction

309. The Program Counter (PC):

1. Is a register
2. During execution of the current instruction, its content changes
3. Both (A) and (B)
4. None of the above

310. The TRAP interrupt mechanism of the 8085 microprocessor executes:

1. An RST by hardware
2. The instructions supplied by external device through the INTA signal
3. An instruction from memory location 20H
4. None of the above

311. Pseudo-instructions are:

1. Assembler directives
2. Instructions in any program that have no corresponding machine code instruction
3. Instruction in any program whose presence or absence will not change the output for any input
4. None of the above

312. “The number of instructions needed to add ‘n’ numbers and store the result in memory using only one address instructions is:

1. n
2. n-1
3. n+1
4. Independent of n

313. The addressing mode used in the instruction PUSH B is:

1. Direct
2. Register indirect
3. Register
4. Immediate

314. The process of fetching and executing instructions one at a time, in order to increasing an address is called:

1. Instruction execution
2. Instruction fetch
3. Straight line sequencing
4. Random sequencing

315. The CPU of a computer takes instruction from the memory and executes them. This process is called:

1. Load cycle
2. Fetch-execute cycle
3. Time sequence
4. Clock cycle

316. In a microprocessor, WAIT states are used to:

1. Make the processor wait during a DMA operation
2. Make the processor wait during a power interrupt processing
3. Make the processor wait during a power shutdown
4. Interface slow peripheral to the processor

317. When a program is being executed in an 8085 microprocessor, its program counter contains:

1. Number of instructions in the current program that have already been executed
2. The total number of instructions in the program being executed
3. Memory address of the instructions that is being currently executed
4. Memory address of the instructions that is to be executed next

318. When the HLT instructions of an 8085 microprocessor is executed, the microprocessor:

1. Is disconnected from the system bus till the reset is pressed
2. Halts execution of the program and returns to monitor
3. Enters into a halt-state and the buses are tri-stated
4. Reloads the program from the location 0024 and 0025

319. Serial input data of 8085 can be loaded into bit 7 of the accumulator by:

1. Executing a RIM instruction
2. Using TRAP
3. Executing RST 1
4. None of the above

320. Which of the following interrupts are unmaskable interrupts?

1. RST 5.5
2. TRAP
3. RST 7.5
4. INTR 1

321. The memory address ranges to which RAM will respond:

1. 0000 H to 1 FFF H
2. 4000 H to 5 FFF H
3. 0000 H to 5 FFF H
4. 3000 H to FFFF H

322. The address range to which I/O chip will respond is:

1. 0000 H to FFFF H
2. 4000H to 5FFF H
3. 0000H to 5FFFH
4. 3000 H to FFFF H

323. Both the arithmetic logic unit (ALU) and control section of CPU employ special purpose storage location called:

1. Decoder
2. Multiplexer
3. Buffers
4. Registers

324. A basic instruction that can be interpreted by a computer generally has:

1. An operand and an address
2. Sequence register and decoder
3. A decoder and an accumulator
4. An address and decoder

325. The differences between PLA and ROM is:

1. PLA is combination ROM is sequential
2. PLA economizes on the number of minterms
3. PLA has fixed AND array, ROM has fixed OR array
4. None of these

326. The control unit of computer:

1. Performs ALU operations on the data
2. Controls the operation of the output devices
3. Is a device for manually operating the computer
4. Directs the other unit of computers

327. The ALU of a computer normally contains a number of high-speed storage elements called:

1. Semiconductor memory
2. Hard disk
3. Registers
4. Magnetic disks

328. The unit of a computer system which executes program, communication with and often controls the operation of other subsystems of the computer is the:

1. CPU
2. I/O unit
3. Control unit
4. Peripheral unit

329. The ability of a medium size computer system to increase in data processing capability by addition of such devices as mass storage device, I/O device etc. is called:

1. Computer expandability
2. Computer enhancement
3. Computer mobility
4. Computer upward capability

330. The technique which repeatedly uses the same block of internal storage during different stage of problem is called:

1. Overlay
2. Swapping
3. Overlapping
4. Reuse

331. The registers used as a working area in CPU is:

1. Program counter
2. Instruction decoder
3. Instruction register
4. Accumulator

332. Which of the following information holds the information before going to the decoder?

1. Control register
2. Accumulator
3. Data register
4. Address register

333. Which of the following unit is used to supervise each instruction in the CPU?

1. Control logic unit
2. ALU
3. Accumulator
4. Control register

334. The bus which is used to transfer data from main memory to peripheral device is:

1. Data bus
2. DMA bus
3. Input bus
4. Output bus

335. The device which is used to connect a peripheral to bus is called:

1. Control register
2. Communication protocol
3. Interface
4. None of these

336. The bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is called:

1. DMA bus
2. Address bus
3. Memory bus
4. Control bus

337. What is the storage capacity of a Hollerith card which is organized into nibbles?

1. 32
2. 120
3. 64
4. 240

338. How many addresses are required for 25x40 video RAM?

1. 1020
2. 1000
3. 1920
4. 2000

339. Microprogramming is a technique for:

1. Writing small program effectively
2. Programming output/input routines
3. Programming the microprocessor
4. Programming the control steps of a computer

340. A device that works in conjunction with a computer but not as part of it is called:

1. Microprocessor
2. Hardware
3. Peripheral device
4. Memory

341. A system of letters, numbers symbols adopted by computer manufacture as an abbreviation form of instruction sets is called

1. Mesh
2. Modern
3. Monitor
4. Mnemonic

342. When a subroutine is called, then address of the instruction following the CALL instruction is stored in/on the

1. Stack pointer
2. Program counter
3. Accumulator
4. Stack

343. In 8085 microprocessors, the value of the most significant bit of the result following the execution of any arithmetic or Boolean instruction is stored in the

1. Carry status flag
2. Sign status flag
3. Auxiliary carry status flag
4. Zero status flag

344. PLA

1. Produces sum of products as the outputs
2. Is dedicated for a particular operation
3. Is general
4. Both A and B

345. The sequence of events that happen during a typical fetch operation is

1. PC-MAR-Memory-MDR-IR
2. PC-Memory-IR
3. PC-Memory-MDR-IR
4. PC-MAR-Memory-IR

346. Which of the following is not a form of memory?

1. Instruction cache
2. Instruction opcode
3. Instruction register
4. Translation lookaside buffer

347. Which memory is difficult to interface with processor?

1. Static memory
2. ROM
3. Dynamic memory
4. RAM

348. Desirable characteristic(s) of a memory system is(are)

1. Speed and reliability
2. Durability and compactness
3. Low power consumption
4. All of these

349. The minimum time delay required between initiation of two successive memory operation is called

1. Memory cycle time
2. Transmission time
3. Memory access time
4. Skip time

350. Which of the following statement is wrong?

1. RAM is a type of volatile
2. Magnetic tape is non-volatile
3. Magnetic core and semiconductor memories are used as mass memory medium
4. An EPROM can be programmed, erased and reprogrammed by user with an EPROM programming instruction