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LicenseComputer4. Computer-organization-and-embedded-systemMCQsset-10

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451. Address symbol table is generated by

  1. Memory management software
  2. Assembler
  3. Match logic of associative memory
  4. Generated by operating system
Show me the answer

Answer: 2. Assembler

Explanation:

  • The address symbol table is generated by the assembler during the assembly process. It maps symbolic addresses to their corresponding memory addresses.

452. When an instruction is read from the memory, it is called

  1. Memory read cycle
  2. Fetch cycle
  3. Instruction cycle
  4. Memory write cycle
Show me the answer

Answer: 2. Fetch cycle

Explanation:

  • The fetch cycle is the process of retrieving an instruction from memory. It is the first step in the instruction cycle.

453. Which activity does not take place during execution cycle?

  1. ALU performs the arithmetic and logical operation
  2. Effective address is calculated
  3. Next instruction is fetched
  4. Branch address is calculated and branching conditions are checked
Show me the answer

Answer: 3. Next instruction is fetched

Explanation:

  • The next instruction is fetched during the fetch cycle, not the execution cycle. The execution cycle involves performing operations like ALU calculations, effective address calculation, and branching.

454. The time for which the D-input of a D-FF must not change after the clock is applied is known as

  1. Hold time
  2. Set-up time
  3. Transition time
  4. Delay time
Show me the answer

Answer: 1. Hold time

Explanation:

  • Hold time is the minimum time for which the input (D-input) must remain stable after the clock edge to ensure proper operation of the flip-flop.

455. How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16?

  1. 64
  2. 16
  3. 32
  4. 128
Show me the answer

Answer: 1. 64

Explanation:

  • Each chip provides 128 x 8 bits = 1024 bits. For 4096 x 16 bits = 65536 bits, the number of chips required is 65536 / 1024 = 64.

456. In addition of two signed numbers, represented in 2’s complement form generates an overflow if

  1. A. B = 0
  2. A = 0
  3. A. B = 1
  4. A + B = 1
Show me the answer

Answer: 3. A. B = 1

Explanation:

  • Overflow occurs in 2’s complement addition if the sign bits of the operands are the same but differ from the sign bit of the result.

457. In DMA the data transfer is controlled by…

  1. Microprocessor
  2. RAM
  3. Memory
  4. I/O devices
Show me the answer

Answer: 4. I/O devices

Explanation:

  • In DMA (Direct Memory Access), data transfer is controlled by I/O devices, bypassing the CPU to directly access memory.

458. Synchronous means…

  1. At irregular intervals
  2. At same time
  3. At variable time
  4. None of the above
Show me the answer

Answer: 2. At same time

Explanation:

  • Synchronous operations occur at the same time or are coordinated by a clock signal.

459. Excess-3 equivalent representation of (1234) H is

  1. (1237) Ex-3
  2. (4567) Ex-3
  3. (7993) Ex-3
  4. (4663) Ex-3
Show me the answer

Answer: 2. (4567) Ex-3

Explanation:

  • Excess-3 code is obtained by adding 3 to each digit of the hexadecimal number. For (1234)H, the Excess-3 equivalent is (4567)Ex-3.

460. Which of the memory holds the information when the Power Supply is switched off?

  1. Static RAM
  2. Dynamic RAM
  3. EEROM
  4. None of the above
Show me the answer

Answer: 3. EEROM

Explanation:

  • EEROM (Electrically Erasable Read-Only Memory) retains data even when the power is switched off, unlike volatile memories like SRAM and DRAM.

461. Minimum no. of NAND gate required implementing an Ex-OR function is

  1. 2
  2. 3
  3. 4
  4. 5
Show me the answer

Answer: 3. 4

Explanation:

  • A minimum of 4 NAND gates are required to implement an XOR function.

462. Which of the following expression is not equivalent to x?

  1. x NAND x
  2. x NOR x
  3. x NAND 1
  4. x NOR 1
Show me the answer

Answer: 4. x NOR 1

Explanation:

  • The expression x NOR 1 is equivalent to NOT x, which is not the same as x.

463. BCD equivalent of Two’s complement is

  1. Nine’s complement
  2. One’s complement+1
  3. Ten’s complement
  4. None of the above
Show me the answer

Answer: 3. Ten’s complement

Explanation:

  • The BCD equivalent of Two’s complement is Ten’s complement.

464. Associative memory is sometimes called as…

  1. Virtual memory
  2. Cache memory
  3. Main memory
  4. Content addressable memory
Show me the answer

Answer: 4. Content addressable memory

Explanation:

  • Associative memory is also known as Content Addressable Memory (CAM), where data is accessed based on its content rather than an address.

465. When CPU is not fully loaded, which of the following method of data transfer is preferred?

  1. DMA
  2. Interrupt
  3. Polling
  4. None of the above
Show me the answer

Answer: 2. Interrupt

Explanation:

  • When the CPU is not fully loaded, interrupt-driven data transfer is preferred as it allows the CPU to handle other tasks while waiting for I/O operations.

466. 8085 microprocessor carryout the subtraction by

  1. BCD subtraction method
  2. Hexadecimal subtraction method
  3. 2’s complement method
  4. Floating Point subtraction method
Show me the answer

Answer: 3. 2’s complement method

Explanation:

  • The 8085 microprocessor performs subtraction using the 2’s complement method.

467. PAL circuit consists of

  1. Fixed OR & programmable AND logic
  2. Programmable OR & Fixed AND Logic
  3. Fixed OR & fixed AND logic
  4. Programmable OR & programmable AND logic
Show me the answer

Answer: 1. Fixed OR & programmable AND logic

Explanation:

  • PAL (Programmable Array Logic) consists of a fixed OR array and a programmable AND array.

468. CPU checks for an interrupt signal during

  1. Starting of last Machine cycle
  2. First T-State of interrupt cycle
  3. Last T-State of instruction cycle
  4. Fetch cycle
Show me the answer

Answer: 3. Last T-State of instruction cycle

Explanation:

  • The CPU checks for interrupt signals during the last T-State of the instruction cycle.

469. Which of the following is not a characteristic of RISC architecture…?

  1. Larger instruction set
  2. Simple addressing mode
  3. One instruction per cycle
  4. Register to register operation
Show me the answer

Answer: 1. Larger instruction set

Explanation:

  • RISC architecture is characterized by a smaller instruction set, not a larger one.

470. Memory interleaving technique is used to address the memory modules in order to have

  1. Higher average utilization
  2. Faster access to a block of data
  3. Reduced complexity in mapping hardware
  4. Both (A) and (B)
Show me the answer

Answer: 4. Both (A) and (B)

Explanation:

  • Memory interleaving improves average utilization and provides faster access to data blocks by distributing memory accesses across multiple modules.

471. In a multiprogramming system, which of the following is used?

  1. Data parallelism
  2. L1 cache
  3. Paging concept
  4. None of the above
Show me the answer

Answer: 3. Paging concept

Explanation:

  • Multiprogramming systems use the paging concept to manage memory efficiently and allow multiple programs to run concurrently.

472. Cycle stealing technique is used in

  1. Interrupt based data transfer
  2. DMA based data transfer
  3. Polled mode data transfer
  4. None of the above
Show me the answer

Answer: 2. DMA based data transfer

Explanation:

  • Cycle stealing is a technique used in DMA (Direct Memory Access) where the DMA controller temporarily takes control of the bus to transfer data.

473. During DMA acknowledge cycle, CPU relinquishes

  1. Address bus only
  2. Control bus and data bus
  3. Address bus and control bus
  4. Data bus and address bus
Show me the answer

Answer: 4. Data bus and address bus

Explanation:

  • During a DMA acknowledge cycle, the CPU relinquishes control of the data bus and address bus to the DMA controller.

474. If the stack pointer is initialized with (4FEB) H, then after execution of Push operation in 8085 microprocessors, the Stack Pointer shall be

  1. 4FEA
  2. 4FEC
  3. 4FED
  4. 4FE9
Show me the answer

Answer: 1. 4FEA

Explanation:

  • In the 8085 microprocessor, the stack pointer decrements by 2 after a push operation. So, 4FEB - 2 = 4FEA.

475. A more efficient way to organize a Page Table is by means of an associative memory having

  1. Number of words equal to number of pages
  2. Number of words more than the number of pages
  3. Number of words less than the number of pages
  4. Any one of the above
Show me the answer

Answer: 1. Number of words equal to number of pages

Explanation:

  • An associative memory (like a TLB) is most efficient when the number of words equals the number of pages.

476. If there are four ROM ICs of 8K and two RAM ICs of 4K words, then the address range of 1st RAM is (Assume initial addresses correspond to ROMs)

  1. (8000) H to (9FFF) H
  2. (8000) H to (8FFF) H
  3. (6000) H to (7FFF) H
  4. (9000) H to (9FFF) H
Show me the answer

Answer: 2. (8000) H to (8FFF) H

Explanation:

  • The first RAM starts after the ROMs. Since ROMs occupy 32K (4 x 8K), the RAM starts at 8000H and ends at 8FFFH.

477. A.B.C is equal to A B C for

  1. A=0, B=1, C=0
  2. A=1, B=0, C=1
  3. A=1, B=1, C=1
  4. All of the above
Show me the answer

Answer: 4. All of the above

Explanation:

  • The expression A.B.C is equivalent to A B C for all combinations of A, B, and C.

478. Gray code equivalent of (1000)2 is

  1. 1111
  2. 1100
  3. 1000
  4. None of the above
Show me the answer

Answer: 2. 1100

Explanation:

  • The Gray code equivalent of binary 1000 is 1100.

479. The memory blocks are mapped on to the cache with the help of…

  1. Hash functions
  2. Vectors
  3. Mapping functions
  4. None of the above
Show me the answer

Answer: 3. Mapping functions

Explanation:

  • Memory blocks are mapped to cache using mapping functions like direct, associative, or set-associative mapping.

480. During a write operation if the required block is not present in the cache then… occurs

  1. Write latency
  2. Write hit
  3. Write delay
  4. Write miss
Show me the answer

Answer: 4. Write miss

Explanation:

  • A write miss occurs when the required block is not present in the cache during a write operation.

481. In… protocol the information is directly written into main…

  1. Write through
  2. Write back
  3. Write first
  4. None of the above
Show me the answer

Answer: 1. Write through

Explanation:

  • In the write-through protocol, data is written directly to both the cache and the main memory.

482. The method of mapping the consecutive memory blocks to consecutive cache blocks is called…

  1. Set associative
  2. Associative
  3. Direct
  4. Indirect
Show me the answer

Answer: 3. Direct

Explanation:

  • Direct mapping maps consecutive memory blocks to consecutive cache blocks in a fixed manner.

483. While using the direct mapping technique, in a 16-bit system the higher order 5 bits is used for…

  1. Tag
  2. Block
  3. Word
  4. Id
Show me the answer

Answer: 1. Tag

Explanation:

  • In direct mapping, the higher-order bits are used as the tag to identify the memory block.

484. The technique of searching for a block by going through all tags is…

  1. Linear search
  2. Binary search
  3. Associative search
  4. None of the above
Show me the answer

Answer: 3. Associative search

Explanation:

  • Associative search involves comparing all tags simultaneously to find a match.

485. In case of Zero-address instruction method the operands are stored in…

  1. Register
  2. Accumulators
  3. Push down stack
  4. Cache
Show me the answer

Answer: 3. Push down stack

Explanation:

  • In zero-address instructions, operands are stored in a push-down stack.

486. The addressing mode which makes use of in-direction pointer is…

  1. Indirect addressing mode
  2. Index addressing mode
  3. Relative addressing mode
  4. Offset addressing mode
Show me the answer

Answer: 1. Indirect addressing mode

Explanation:

  • Indirect addressing mode uses a pointer to the memory location where the actual operand is stored.

487. The addressing mode, where you directly specify the operand value is

  1. Immediate
  2. Direct
  3. Definite
  4. Relative
Show me the answer

Answer: 1. Immediate

Explanation:

  • Immediate addressing mode directly specifies the operand value in the instruction.

488. …addressing mode is most suitable to change the normal sequence of execution of instructions.

  1. Relative
  2. Indirect
  3. Index with offset
  4. Immediate
Show me the answer

Answer: 1. Relative

Explanation:

  • Relative addressing mode is used to change the normal sequence of execution by specifying an offset from the current instruction pointer.

489. The pipelining process is also called as…

  1. Superscalar operation
  2. Assembly line operation
  3. Von Neumann cycle
  4. None of the mentioned
Show me the answer

Answer: 2. Assembly line operation

Explanation:

  • Pipelining is often compared to an assembly line, where multiple stages of instruction execution overlap.

490. The fetch and execution cycles are interleaved with the help of…

  1. Modification in processor architecture
  2. Clock
  3. Special unit
  4. Control unit
Show me the answer

Answer: 2. Clock

Explanation:

  • The clock synchronizes the fetch and execution cycles, allowing them to interleave efficiently.

491. The situation where in the data of operands are not available is called…

  1. Data hazard
  2. Stock
  3. Deadlock
  4. Structural hazard
Show me the answer

Answer: 1. Data hazard

Explanation:

  • A data hazard occurs when the data required for an instruction is not yet available.

492. The reason for the implementation of the cache memory is

  1. To increase the internal memory of the system
  2. The difference in speeds of operation of the processor and memory
  3. To reduce the memory access and cycle time
  4. All of the above
Show me the answer

Answer: 2. The difference in speeds of operation of the processor and memory

Explanation:

  • Cache memory is implemented to bridge the speed gap between the processor and main memory.

493. The effectiveness of the cache memory is based on the property of ______.

  1. Locality of reference
  2. Memory localization
  3. Memory size
  4. None of the above
Show me the answer

Answer: 1. Locality of reference

Explanation:

  • Cache memory leverages the principle of locality of reference, where programs tend to access the same data or nearby data repeatedly.

494. The temporal aspect of the locality of reference means

  1. That the recently executed instruction won’t be executed soon
  2. That the recently executed instruction is temporarily not referenced
  3. That the recently executed instruction will be executed soon again
  4. None of the above
Show me the answer

Answer: 3. That the recently executed instruction will be executed soon again

Explanation:

  • Temporal locality refers to the tendency of a program to reuse the same data or instructions in the near future.

495. The spatial aspect of the locality of reference means

  1. That the recently executed instruction is executed again next
  2. That the recently executed won’t be executed again
  3. That the instruction executed will be executed at a later time
  4. That the instruction in close proximity of the instruction executed will be executed in future
Show me the answer

Answer: 4. That the instruction in close proximity of the instruction executed will be executed in future

Explanation:

  • Spatial locality refers to the tendency of a program to access data or instructions that are close to recently accessed data.

496. The algorithm to remove and place new contents into the cache is called ______.

  1. Renewal algorithm
  2. Updating
  3. Replacement algorithm
  4. None of the above
Show me the answer

Answer: 3. Replacement algorithm

Explanation:

  • The replacement algorithm determines which cache block to replace when new data needs to be loaded.

497. The key factor/s in commercial success of a computer is/are…

  1. Performance
  2. Cost
  3. Speed
  4. Both A and B
Show me the answer

Answer: 4. Both A and B

Explanation:

  • The commercial success of a computer depends on both performance and cost.

498. The main objective of the computer system is

  1. To provide optimal power operation
  2. To provide best performance at low cost
  3. To provide speedy operation at low power consumption
  4. All of the above
Show me the answer

Answer: 2. To provide best performance at low cost

Explanation:

  • The primary objective of a computer system is to deliver the best performance at the lowest possible cost.

499. A common measure of performance is:

  1. Price/performance ratio
  2. Performance /price ratio
  3. Operation/price ratio
  4. None of the above
Show me the answer

Answer: 1. Price/performance ratio

Explanation:

  • The price/performance ratio is a common metric used to evaluate the efficiency of a computer system.

500. The main purpose of having memory hierarchy is to

  1. Reduce access time
  2. Provide large capacity
  3. Reduce propagation time
  4. Both A and B
Show me the answer

Answer: 4. Both A and B

Explanation:

  • Memory hierarchy aims to reduce access time and provide large storage capacity.
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