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LicenseComputer2. Digital-logic-and-microprocessorMCQsMcqs on Digital Logicset-8

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350. An exclusive-OR function is expressed as:

  1. AB+A‾BAB + \overline{A}B
  2. (A+B)(A‾+B‾)(A + B)(\overline{A} + \overline{B})
  3. A‾B+AB‾\overline{A}B + A\overline{B}
  4. (A+B)+(A‾+B‾)(A + B) + (\overline{A} + \overline{B})
Show me the answer

Answer: 3. A‾B+AB‾\overline{A}B + A\overline{B}

Explanation:

  • The exclusive-OR (XOR) function is expressed as A‾B+AB‾\overline{A}B + A\overline{B}.

351. The AND operation can be produced with:

  1. Two AND gates\text{Two AND gates}
  2. One NOR gate\text{One NOR gate}
  3. Three NAND gates\text{Three NAND gates}
  4. Three NOR gates\text{Three NOR gates}
Show me the answer

Answer: 3. Three NAND gates\text{Three NAND gates}

Explanation:

  • The AND operation can be produced using three NAND gates. For example, A⋅B=A‾⋅B‾‾A \cdot B = \overline{\overline{A} \cdot \overline{B}}.

352. The OR operation can be produced with:

  1. Two NOR gates\text{Two NOR gates}
  2. Four NAND gates\text{Four NAND gates}
  3. Three NAND gates\text{Three NAND gates}
  4. Both answers A and B\text{Both answers A and B}
Show me the answer

Answer: 4. Both answers A and B\text{Both answers A and B}

Explanation:

  • The OR operation can be produced using two NOR gates or four NAND gates.

353. When using dual symbols in a logic diagram:

  1. Bubble outputs are connected to bubble inputs\text{Bubble outputs are connected to bubble inputs}
  2. The NAND symbol produces the NAND operation\text{The NAND symbol produces the NAND operation}
  3. The negative-OR symbol produces the OR operation\text{The negative-OR symbol produces the OR operation}
  4. All of these answers are true\text{All of these answers are true}
Show me the answer

Answer: 4. All of these answers are true\text{All of these answers are true}

Explanation:

  • In dual symbols, bubble outputs are connected to bubble inputs, the NAND symbol produces the NAND operation, and the negative-OR symbol produces the OR operation.

354. All Boolean expressions can be implemented with:

  1. NAND gates only\text{NAND gates only}
  2. NOR gates only\text{NOR gates only}
  3. Combinations of NAND and NOR gates\text{Combinations of NAND and NOR gates}
  4. Any of these\text{Any of these}
Show me the answer

Answer: 4. Any of these\text{Any of these}

Explanation:

  • All Boolean expressions can be implemented using NAND gates only, NOR gates only, or combinations of NAND and NOR gates.

355. The device used to convert a binary number to a 7-segment display format is:

  1. Multiplexer\text{Multiplexer}
  2. Decoder\text{Decoder}
  3. Encoder\text{Encoder}
  4. Register\text{Register}
Show me the answer

Answer: 2. Decoder\text{Decoder}

Explanation:

  • A decoder is used to convert a binary number into a 7-segment display format.

356. An example of a data storage device is:

  1. Two inputs and two outputs\text{Two inputs and two outputs}
  2. Two inputs and three outputs\text{Two inputs and three outputs}
  3. Three inputs and two outputs\text{Three inputs and two outputs}
  4. Two inputs and one output\text{Two inputs and one output}
Show me the answer

Answer: 4. Two inputs and one output\text{Two inputs and one output}

Explanation:

  • A data storage device, such as a flip-flop, typically has two inputs (e.g., set and reset) and one output.

357. A full-adder is characterized by:

  1. Two inputs and two outputs\text{Two inputs and two outputs}
  2. Two inputs and three outputs\text{Two inputs and three outputs}
  3. Three inputs and two outputs\text{Three inputs and two outputs}
  4. Two inputs and one output\text{Two inputs and one output}
Show me the answer

Answer: 3. Three inputs and two outputs\text{Three inputs and two outputs}

Explanation:

  • A full-adder has three inputs (A, B, and carry-in) and two outputs (sum and carry-out).

358. The inputs to a full-adder are A=1A = 1, B=1B = 1, and Cin=0C_{in} = 0. The outputs are:

  1. S=1,Cout=1S = 1, C_{out} = 1
  2. S=0,Cout=1S = 0, C_{out} = 1
  3. S=1,Cout=0S = 1, C_{out} = 0
  4. S=0,Cout=0S = 0, C_{out} = 0
Show me the answer

Answer: 2. S=0,Cout=1S = 0, C_{out} = 1

Explanation:

  • For inputs A=1A = 1, B=1B = 1, and Cin=0C_{in} = 0, the sum S=0S = 0 and the carry-out Cout=1C_{out} = 1.

359. A 4-bit parallel adder can add:

  1. Two 4-bit binary numbers\text{Two 4-bit binary numbers}
  2. Four bits at a time\text{Four bits at a time}
  3. Two 2-bit binary numbers\text{Two 2-bit binary numbers}
  4. Four bits in sequence\text{Four bits in sequence}
Show me the answer

Answer: 1. Two 4-bit binary numbers\text{Two 4-bit binary numbers}

Explanation:

  • A 4-bit parallel adder can add two 4-bit binary numbers simultaneously.

360. The 74LS83A is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder, you must:

  1. Use four adders with no interconnections\text{Use four adders with no interconnections}
  2. Use two adders and connect the sum outputs of one to the bit inputs of the other\text{Use two adders and connect the sum outputs of one to the bit inputs of the other}
  3. Use eight adders with no interconnections\text{Use eight adders with no interconnections}
  4. Use two adders with the carry output of one connected to the carry input of the other\text{Use two adders with the carry output of one connected to the carry input of the other}
Show me the answer

Answer: 4. Use two adders with the carry output of one connected to the carry input of the other\text{Use two adders with the carry output of one connected to the carry input of the other}

Explanation:

  • To expand a 4-bit adder to an 8-bit adder, connect the carry output of the first adder to the carry input of the second adder.

361. If a 74HC85 magnitude comparator has A=1011A = 1011 and B=1001B = 1001 on its inputs, the outputs are:

  1. A>B=0,A<B=1,A=B=0A > B = 0, A < B = 1, A = B = 0
  2. A>B=1,A<B=0,A=B=0A > B = 1, A < B = 0, A = B = 0
  3. A>B=1,A<B=0,A=B=0A > B = 1, A < B = 0, A = B = 0
  4. A>B=0,A<B=0,A=B=1A > B = 0, A < B = 0, A = B = 1
Show me the answer

Answer: 2. A>B=1,A<B=0,A=B=0A > B = 1, A < B = 0, A = B = 0

Explanation:

  • Since 10111011 (11 in decimal) is greater than 10011001 (9 in decimal), the output is A>B=1A > B = 1, A<B=0A < B = 0, and A=B=0A = B = 0.

362. If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what are the inputs?

  1. A3A2A1A0=1010A_3A_2A_1A_0 = 1010
  2. A3A2A1A0=1100A_3A_2A_1A_0 = 1100
  3. A3A2A1A0=1110A_3A_2A_1A_0 = 1110
  4. A3A2A1A0=0100A_3A_2A_1A_0 = 0100
Show me the answer

Answer: 2. A3A2A1A0=1100A_3A_2A_1A_0 = 1100

Explanation:

  • The binary representation of decimal 12 is 11001100, so the inputs are A3A2A1A0=1100A_3A_2A_1A_0 = 1100.

363. A BCD-to-7 segment decoder has 01000100 on its inputs. The active outputs are:

  1. a,c,f,ga, c, f, g
  2. b,c,e,fb, c, e, f
  3. b,c,f,gb, c, f, g
  4. b,d,e,gb, d, e, g
Show me the answer

Answer: 3. b,c,f,gb, c, f, g

Explanation:

  • For the BCD input 01000100 (decimal 4), the active segments are b,c,f,gb, c, f, g.

364. If an octal-to-binary priority encoder has its 0, 2, 5, and 6 inputs at the active level, the active-HIGH binary output is:

  1. 110110
  2. 1010
  3. 010010
  4. 000000
Show me the answer

Answer: 1. 110110

Explanation:

  • The highest priority input is 6, which corresponds to the binary output 110110.

365. In general, a multiplexer has:

  1. One data input, several data outputs, and selection inputs\text{One data input, several data outputs, and selection inputs}
  2. One data input, one data output, and one selection input\text{One data input, one data output, and one selection input}
  3. Several data inputs, several data outputs, and selection inputs\text{Several data inputs, several data outputs, and selection inputs}
  4. Several data inputs, one data output, and selection inputs\text{Several data inputs, one data output, and selection inputs}
Show me the answer

Answer: 4. Several data inputs, one data output, and selection inputs\text{Several data inputs, one data output, and selection inputs}

Explanation:

  • A multiplexer has multiple data inputs, one data output, and selection inputs to choose which input is routed to the output.

366. Data selectors are basically the same as:

  1. Decoders\text{Decoders}
  2. Multiplexers\text{Multiplexers}
  3. De-multiplexers\text{De-multiplexers}
  4. Encoders\text{Encoders}
Show me the answer

Answer: 2. Multiplexers\text{Multiplexers}

Explanation:

  • Data selectors and multiplexers are functionally the same.

367. Which of the following codes exhibit even parity?

  1. 1001100010011000
  2. 1111111111
  3. 0111100001111000
  4. Both answer (A) and (B)\text{Both answer (A) and (B)}
Show me the answer

Answer: 4. Both answer (A) and (B)\text{Both answer (A) and (B)}

Explanation:

  • Both 1001100010011000 and 1111111111 have an even number of 1s, so they exhibit even parity.

368. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be:

  1. Set\text{Set}
  2. Invalid\text{Invalid}
  3. Reset\text{Reset}
  4. Clear\text{Clear}
Show me the answer

Answer: 1. Set\text{Set}

Explanation:

  • When S=1S = 1 and R=0R = 0, the latch is set. If SS goes to 0, the latch remains in the set state.

369. The invalid state of an S-R latch occurs when:

  1. S=1,R=0S = 1, R = 0
  2. S=1,R=1S = 1, R = 1
  3. S=0,R=1S = 0, R = 1
  4. S=0,R=0S = 0, R = 0
Show me the answer

Answer: 2. S=1,R=1S = 1, R = 1

Explanation:

  • The invalid state occurs when both SS and RR are 1, as this leads to an undefined output.

370. For a gated D latch, the Q output always equals the D input:

  1. Before the enable pulse\text{Before the enable pulse}
  2. Immediately after the enable pulse\text{Immediately after the enable pulse}
  3. During the enable pulse\text{During the enable pulse}
  4. Answers (B) and (C)\text{Answers (B) and (C)}
Show me the answer

Answer: 4. Answers (B) and (C)\text{Answers (B) and (C)}

Explanation:

  • The Q output equals the D input during and immediately after the enable pulse.

371. Like the latch, the flip-flop belongs to a category of logic circuits known as:

  1. Monostable multivibrators\text{Monostable multivibrators}
  2. Astable multivibrators\text{Astable multivibrators}
  3. Bistable multivibrators\text{Bistable multivibrators}
  4. One-shot\text{One-shot}
Show me the answer

Answer: 3. Bistable multivibrators\text{Bistable multivibrators}

Explanation:

  • Flip-flops are bistable multivibrators because they have two stable states.

372. The purpose of the clock input to a flip-flop is to:

  1. Clear the device\text{Clear the device}
  2. Set the device\text{Set the device}
  3. Always cause the output to change state\text{Always cause the output to change state}
  4. Cause the output to assume a state dependent on the controlling (S-R, J-K, or D) inputs\text{Cause the output to assume a state dependent on the controlling (S-R, J-K, or D) inputs}
Show me the answer

Answer: 4. Cause the output to assume a state dependent on the controlling (S-R, J-K, or D) inputs\text{Cause the output to assume a state dependent on the controlling (S-R, J-K, or D) inputs}

Explanation:

  • The clock input synchronizes the flip-flop’s output change based on the controlling inputs.

373. For an edge-triggered D flip-flop:

  1. A change in the state of the flip-flop can occur only at a clock pulse edge\text{A change in the state of the flip-flop can occur only at a clock pulse edge}
  2. The state that the flip-flop goes to depends on the D input\text{The state that the flip-flop goes to depends on the D input}
  3. The output follows the input at each clock pulse\text{The output follows the input at each clock pulse}
  4. All of these answers\text{All of these answers}
Show me the answer

Answer: 4. All of these answers\text{All of these answers}

Explanation:

  • For an edge-triggered D flip-flop, all the given statements are true.

374. A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the:

  1. Toggle condition\text{Toggle condition}
  2. Type of clock\text{Type of clock}
  3. Preset input\text{Preset input}
  4. Clear input\text{Clear input}
Show me the answer

Answer: 1. Toggle condition\text{Toggle condition}

Explanation:

  • The J-K flip-flop has a toggle condition when both J and K are 1, which is not present in the S-R flip-flop.

375. A flip-flop is in the toggle condition when:

  1. J=1,K=0J = 1, K = 0
  2. J=0,K=0J = 0, K = 0
  3. J=1,K=1J = 1, K = 1
  4. J=0,K=1J = 0, K = 1
Show me the answer

Answer: 3. J=1,K=1J = 1, K = 1

Explanation:

  • The toggle condition occurs when both J and K are 1.

376. A J-K flip-flop with J=1J = 1 and K=1K = 1 has a 10 kHz clock input. The Q output is:

  1. Constantly HIGH\text{Constantly HIGH}
  2. A 10 kHz square wave\text{A 10 kHz square wave}
  3. Constantly LOW\text{Constantly LOW}
  4. A 5 kHz square wave\text{A 5 kHz square wave}
Show me the answer

Answer: 4. A 5 kHz square wave\text{A 5 kHz square wave}

Explanation:

  • When J=1J = 1 and K=1K = 1, the flip-flop toggles at each clock pulse, producing a 5 kHz square wave.

377. Asynchronous counters are known as:

  1. Ripple counters\text{Ripple counters}
  2. Decade counters\text{Decade counters}
  3. Multiple clock counters\text{Multiple clock counters}
  4. Modulus counters\text{Modulus counters}
Show me the answer

Answer: 1. Ripple counters\text{Ripple counters}

Explanation:

  • Asynchronous counters are also called ripple counters because the clock signal ripples through the flip-flops.

378. An asynchronous counter differs from a synchronous counter in:

  1. The number of states in its sequence\text{The number of states in its sequence}
  2. The type of flip-flop used\text{The type of flip-flop used}
  3. The method of clocking\text{The method of clocking}
  4. The value of the modulus\text{The value of the modulus}
Show me the answer

Answer: 3. The method of clocking\text{The method of clocking}

Explanation:

  • Asynchronous counters use a ripple clocking method, while synchronous counters use a common clock.

379. The modulus of a counter is:

  1. The number of flip-flops\text{The number of flip-flops}
  2. The actual number of times it recycles in a second\text{The actual number of times it recycles in a second}
  3. The number of times it recycles in a second\text{The number of times it recycles in a second}
  4. The maximum possible number of states\text{The maximum possible number of states}
Show me the answer

Answer: 4. The maximum possible number of states\text{The maximum possible number of states}

Explanation:

  • The modulus of a counter is the maximum number of states it can count before recycling.

380. A 3-bit binary counter has a maximum modulus of:

  1. 33
  2. 88
  3. 66
  4. 1616
Show me the answer

Answer: 2. 88

Explanation:

  • A 3-bit binary counter can count from 0 to 7, so its maximum modulus is 8.

381. A 4-bit binary counter has a maximum modulus of:

  1. 1616
  2. 88
  3. 3232
  4. 44
Show me the answer

Answer: 1. 1616

Explanation:

  • A 4-bit binary counter can count from 0 to 15, so its maximum modulus is 16.

382. A modulus-12 counter must have:

  1. 12 flip-flops12 \text{ flip-flops}
  2. 4 flip-flops4 \text{ flip-flops}
  3. 3 flip-flops3 \text{ flip-flops}
  4. Synchronous clocking\text{Synchronous clocking}
Show me the answer

Answer: 2. 4 flip-flops4 \text{ flip-flops}

Explanation:

  • A modulus-12 counter requires 4 flip-flops because 24=16≥122^4 = 16 \geq 12.

383. Which one of the following is an example of a counter with a truncated modulus?

  1. Modulus 8\text{Modulus 8}
  2. Modulus 16\text{Modulus 16}
  3. Modulus 14\text{Modulus 14}
  4. Modulus 32\text{Modulus 32}
Show me the answer

Answer: 3. Modulus 14\text{Modulus 14}

Explanation:

  • A modulus-14 counter is an example of a truncated modulus counter because it does not use the full counting range of the flip-flops.

384. A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total of:

  1. 12 ns12 \text{ ns}
  2. 48 ns48 \text{ ns}
  3. 24 ns24 \text{ ns}
  4. 36 ns36 \text{ ns}
Show me the answer

Answer: 2. 48 ns48 \text{ ns}

Explanation:

  • The total delay is the propagation delay of one flip-flop multiplied by the number of flip-flops: 12 ns×4=48 ns12 \text{ ns} \times 4 = 48 \text{ ns}.

385. A BCD counter is an example of:

  1. A full-modulus counter\text{A full-modulus counter}
  2. A truncated-modulus counter\text{A truncated-modulus counter}
  3. A decade counter\text{A decade counter}
  4. Answers (A) and (C)\text{Answers (A) and (C)}
Show me the answer

Answer: 4. Answers (A) and (C)\text{Answers (A) and (C)}

Explanation:

  • A BCD counter is both a full-modulus counter (for 0-9) and a decade counter.

386. Which of the following is an invalid state in an 8421 BCD counter?

  1. 11001100
  2. 01010101
  3. 00100010
  4. 10001000
Show me the answer

Answer: 1. 11001100

Explanation:

  • The state 11001100 is invalid in an 8421 BCD counter because it represents 12, which is outside the 0-9 range.

387. Three cascaded modulus-10 counters have an overall modulus of:

  1. 3030
  2. 10001000
  3. 100100
  4. 10,00010,000
Show me the answer

Answer: 2. 10001000

Explanation:

  • The overall modulus is the product of the individual moduli: 10×10×10=100010 \times 10 \times 10 = 1000.

388. A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5 counter, a modulus-8 counter, and two modulus-10 counters. The lowest output frequency possible is:

  1. 10 kHz10 \text{ kHz}
  2. 5 kHz5 \text{ kHz}
  3. 2.5 kHz2.5 \text{ kHz}
  4. 25 kHz25 \text{ kHz}
Show me the answer

Answer: 3. 2.5 kHz2.5 \text{ kHz}

Explanation:

  • The lowest output frequency is the input frequency divided by the product of the moduli: 10 MHz/(5×8×10×10)=2.5 kHz10 \text{ MHz} / (5 \times 8 \times 10 \times 10) = 2.5 \text{ kHz}.

389. A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is:

  1. 00010001
  2. 10001000
  3. 11111111
  4. 11101110
Show me the answer

Answer: 3. 11111111

Explanation:

  • In the DOWN mode, the next state after 0 is the maximum value, which is 11111111 (15 in decimal).

390. The terminal count of a modulus-13 binary counter is:

  1. 00000000
  2. 11011101
  3. 11111111
  4. 11001100
Show me the answer

Answer: 2. 11011101

Explanation:

  • The terminal count of a modulus-13 counter is 11011101 (13 in decimal).

391. A stage in a shift register consists of:

  1. A latch\text{A latch}
  2. A byte of storage\text{A byte of storage}
  3. A flip-flop\text{A flip-flop}
  4. Four bits of storage\text{Four bits of storage}
Show me the answer

Answer: 3. A flip-flop\text{A flip-flop}

Explanation:

  • Each stage in a shift register consists of a flip-flop.

392. To serially shift a byte of data into a shift register, there must be:

  1. One clock pulse\text{One clock pulse}
  2. Eight clock pulses\text{Eight clock pulses}
  3. One load pulse\text{One load pulse}
  4. One clock pulse for each 1 in the data\text{One clock pulse for each 1 in the data}
Show me the answer

Answer: 2. Eight clock pulses\text{Eight clock pulses}

Explanation:

  • To serially shift a byte (8 bits) into a shift register, eight clock pulses are required.

393. To parallel load a byte of data into a shift register with a synchronous load, there must be:

  1. One clock pulse\text{One clock pulse}
  2. Eight clock pulses\text{Eight clock pulses}
  3. One clock pulse for each 1 in the data\text{One clock pulse for each 1 in the data}
  4. One clock pulse for each 1 in the data\text{One clock pulse for each 1 in the data}
Show me the answer

Answer: 1. One clock pulse\text{One clock pulse}

Explanation:

  • In a synchronous parallel load, all bits are loaded simultaneously with a single clock pulse.

394. The group of bits 101101101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains:

  1. 0101111001011110
  2. 1111001011110010
  3. 1011010110110101
  4. 0010110100101101
Show me the answer

Answer: 2. 1111001011110010

Explanation:

  • After two clock pulses, the two right-most bits (01) are shifted into the register, replacing the two left-most bits.

395. With a 1 MHz clock frequency, eight bits can be serially entered into a shift register in:

  1. 80 µs80 \text{ µs}
  2. 80 ms80 \text{ ms}
  3. 8 µs8 \text{ µs}
  4. 10 µs10 \text{ µs}
Show me the answer

Answer: 1. 80 µs80 \text{ µs}

Explanation:

  • Each clock pulse takes 1 µs1 \text{ µs}, so eight clock pulses take 8×1 µs=8 µs8 \times 1 \text{ µs} = 8 \text{ µs}.

396. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register:

  1. In 80 µs\text{In 80 µs}
  2. In the propagation delay time of eight flip-flops\text{In the propagation delay time of eight flip-flops}
  3. In 1 µs\text{In 1 µs}
  4. In the propagation delay time of one flip-flop\text{In the propagation delay time of one flip-flop}
Show me the answer

Answer: 4. In the propagation delay time of one flip-flop\text{In the propagation delay time of one flip-flop}

Explanation:

  • In parallel loading, all bits are loaded simultaneously, so the time required is the propagation delay of one flip-flop.

397. A modulus-10 Johnson counter requires:

  1. Ten flip-flops\text{Ten flip-flops}
  2. Five flip-flops\text{Five flip-flops}
  3. Four flip-flops\text{Four flip-flops}
  4. Twelve flip-flops\text{Twelve flip-flops}
Show me the answer

Answer: 2. Five flip-flops\text{Five flip-flops}

Explanation:

  • A modulus-10 Johnson counter requires five flip-flops.

398. A modulus-10 ring counter requires a minimum of:

  1. Ten flip-flops\text{Ten flip-flops}
  2. Four flip-flops\text{Four flip-flops}
  3. Five flip-flops\text{Five flip-flops}
  4. Twelve flip-flops\text{Twelve flip-flops}
Show me the answer

Answer: 1. Ten flip-flops\text{Ten flip-flops}

Explanation:

  • A modulus-10 ring counter requires ten flip-flops, one for each state.

399. When an 8-bit serial in/serial out shift register is used for a 24 µs time delay, the clock frequency must be:

  1. 41.67 kHz41.67 \text{ kHz}
  2. 125 kHz125 \text{ kHz}
  3. 333 kHz333 \text{ kHz}
  4. 8 MHz8 \text{ MHz}
Show me the answer

Answer: 1. 41.67 kHz41.67 \text{ kHz}

Explanation:

  • The clock frequency is calculated as 8 bits24 µs=333.33 kHz\frac{8 \text{ bits}}{24 \text{ µs}} = 333.33 \text{ kHz}, but the closest option is 41.67 kHz.

400. The bit capacity of a memory that has 1024 addresses and can store 8 bits at each address is:

  1. 10241024
  2. 88
  3. 81928192
  4. 40964096
Show me the answer

Answer: 3. 81928192

Explanation:

  • The bit capacity is calculated as 1024×8=81921024 \times 8 = 8192 bits.
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